发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF DESIGNING FACILITATION OF ITS INSPECTION
摘要 PROBLEM TO BE SOLVED: To improve the failure detecting ratio of a part having poor observability by probing it twice by one rate of a test pattern. SOLUTION: An optional signal line in a circuit to be inspected is taken as a failure observing position for observing the influence of a failure propagated to the signal line, and an EXOR tree circuit 106 for inputting signal lines 102-104 as the failure observing position is formed. A selector 108 for inputting the output of the EXOR tree circuit 106 and selectively inputting an external input pin 110 is interposed between the circuit to be inspected and the external output pin. For a degeneracy failure assumed in an order circuit which is the circuit to be inspected, the influence of this failure can be easily observed by an external output pin 107.
申请公布号 JPH09243710(A) 申请公布日期 1997.09.19
申请号 JP19960053105 申请日期 1996.03.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HOSOKAWA TOSHINORI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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