JITTER RESTRICTING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a jitter restricting circuit which sufficiently restrict the jitter of a clock based on a byte staff at the time of transmitting data from a synchronization transmitting network to an asynchronization transmitting network. SOLUTION: A writing clock generating part 1 generates a writing clock corresponding only to main signal information of the synchronization transmitting network so as to store it in a buffer memory 2. A byte and bit converting part 3 generates a bit and staff signal where the interval of a bit and staff operation is uniformed from a byte and staff signal and a synchronization clock generating part 6 generates a high-speed clock being synchronized with the synchronization transmitting network clock. Then, a bit and staff part 4 generates a variable frequency-division clock whose frequency division ratio is changed by a bit and staff cycle from the high-speed clock. It is read from the buffer memory 2 by a reading clock which is generated by masding an overhead position so as to execute bit staffing. A smoothing part 5 smoothes the clock of the overhead position by the reading clock so as to output asynchronization transmitting network data.