| 摘要 |
<p>The apparatus (200) includes two memory units (201) having an array of memory cells, an address bus and a crossbar switch (202). One memory unit has an array of memory cells including several redundant cells. The crossbar switch can switch an address addressing a defective cell in the array of an initial memory unit and presented on the address bus to the other memory unit to access a selected redundant cell. The crossbar switch can also modify the address to generate a new address for switching to the second memory unit to access the selected memory cell, or to switch a chip select signal from one memory unit to the other. The arrays may comprise arrays of random access memory cells, or read only memory cells. The memory units may comprise DRAM memories packaged as a single in line memory module.</p> |
