Multiplier with variable resolution for a signal processor

摘要

The multiplier comprises a coarse stage (110) and a fine stage (120) in the signal path. The fine stage has a signal input (121) with 18 bit positions, a control input (122) with 10 positions and an 18-bit output (123) to the storage device (112) of the coarse stage. Another sliding adjuster (130) supplies the control input to the fine stage from a primary control signal (sp) having 18 bit positions. Ten of these form the secondary control signal (sb). To increase resolution, the primary control signal and the output (so) of the coarse stage are weighted by the same power of two in opposite directions.