发明名称 JUNJOKAIRONOKOSHOKASHOSUITEIHOHO
摘要 PURPOSE: To efficiently extract a trouble propagation estimate value and to suppress the error of the estimate value by finally forming a trouble estimate list through estimate processing procedures over several times. CONSTITUTION: Processing procedure extracting the bus/fail pin data of a tester, processing procedure extracting the combination circuit of a semiconductor IC and processing pressure forming the data flow between latches are provided. Further, processing procedure estimating the trouble propagation value of the input part of the combination circuit and extracting the connection data of a rear stage circuit to perform trouble propagation simulation, processing procedure judging whether a simulation result coincides with actual tester bus/fail data to form a latch estimate value table and processing procedure judging whether whole vector estimate processing is completed to estimate the trouble in the combination circuit and judging whether trouble estimate processing is completed are provided.
申请公布号 JP2655105(B2) 申请公布日期 1997.09.17
申请号 JP19940292866 申请日期 1994.11.28
申请人 NIPPON DENKI KK 发明人 ISHAMA TOSHIO;DONARUDO KUREIN
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
代理机构 代理人
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