发明名称 |
System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width |
摘要 |
A processor for processing information is described. The processor can select between a write-burst mode of transferring information and an individual write cycle mode of transferring information. The write-burst mode of transferring information is a transfer of information in a single burst transaction and the individual write cycle mode of transferring information is a transfer of information in separate write cycles.
|
申请公布号 |
US5669014(A) |
申请公布日期 |
1997.09.16 |
申请号 |
US19940297487 |
申请日期 |
1994.08.29 |
申请人 |
INTEL CORPORATION |
发明人 |
IYENGAR, SUNDARAVARATHAN R.;CHOUDHURY, MUSTAFIZ R. |
分类号 |
G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|