| 摘要 |
The present application provides a CMOS device and process in which the source/drain regions are polysilicon, and are dielectrically isolated from the well regions. This structure can be obtained, for example, by depositing the first layer of polysilicon under very high temperature conditions (essentially the same as those normally used for epitaxial deposition), so that the first polysilicon layer is formed epitaxially (as monocrystalline silicon) over exposed regions, and as polycrystalline material over oxide. An oxide is grown on the surface of the deposited layer, and a second polysilicon layer is then deposited, under normal conditions, to form the gate layer. After the second polysilicon layer has been patterned, source/drain implants are then made into the first (intrinsic) polysilicon layer to form source/drain implants. Thus, the first polysilicon layer will contain both N+ and P+ regions, and if desired, may also include intrinsic regions.
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