| 摘要 |
Method of manufacturing VDMOS transistors. The basic steps are described of the process of manufacturing a low-voltage, low-conducting-resistance VDMOS power device. This electrical behaviour is achieved by a triple ion implantation for forming the source 108, drain 106 and short-circuit p+ diffusion 107 regions between the two, followed by the appropriate subsequent heat treatments. The diffusion of boron in the drain region 106 is carried out at a level such that, by maintaining the greatest possible resistivity for it, the breakdown voltage of the device does not substantially decrease. Furthermore, with the object of preventing the activation of the parasitic bipolar transistor inherent to the structure of the VDMOS transistor, the p+ diffusion 107 between source 108 and drain 106 is the surface type, which does not degrade the breakdown voltage of the device for the same thickness of epitaxial layer 102, so that the device's resistance is not altered. <IMAGE>
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