| 摘要 |
PROBLEM TO BE SOLVED: To reduce a drop in the breakdown voltage of a P-N junction between a drain and a substrate and to reduce the degradation of hot melt carriers, by a method wherein an extension region of a complex gate structure is formed of a first layer and a second layer whose impurity concentration is different and of a third layer whose concentration is higher than those of the first and second layers. SOLUTION: An n-type impurity diffusion layer 7 at a concentration of about 1.0×10<21> atoms/cm<3> is formed in the surface of a silicon substrate 1 which is adjacent to the other side of a composite gate structure 32. An n-type impurity layer 8 at a concentration of 5.0×10<20> to 2×10<21> atoms/cm<3> is formed at the outside of the n-type impurity diffusion layer 7 so as to surround the layer 7. In addition, an n-type impurity diffusion layer 9 at a concentration of 1.0×10<18> to 1×10<19> atom/cm<3> is formed at the outside of the n-type impurity layer 8 so as to surround the layer 8. As a result, it is possible to obtain a nonvolatile semiconductor memory device such as an EEERPOM or the like whose rewrite speed is enhanced, in which the breakdown voltage of a P-N junction between a drain and the substrate is enhanced and whose reliability with reference to the degradation of hot carriers is enhanced.
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