| 摘要 |
PCT No. PCT/JP93/00410 Sec. 371 Date Nov. 23, 1994 Sec. 102(e) Date Nov. 23, 1994 PCT Filed Mar. 31, 1993 PCT Pub. No. WO94/23496 PCT Pub. Date Oct. 13, 1994The present invention relates to a fail-safe on-delay circuit which uses an an electronic circuit. An input signal higher than a power source potential is input to a PUT oscillating circuit and a pulse signal generated with a predetermined time constant, is once changed in a level conversion circuit to a level within a range of the power source potential, and then is phase inverted and a rising differential signal of the phase inverted signal is formed. The input signal to the PUT oscillation circuit is applied to one input terminal of a fail-safe two input window comparator, and the differential signal is input to the other input terminal, and self held. After a predetermined delay time an output of logic value 1 is generated from the window comparator. As a result a fail-safe on-delay circuit can be made wherein, in the event of a fault in the elements of the circuit the delay time is not shortened.
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