| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT using a side wall, wherein the TFT is enhanced in offset length, and low-concentration source/ drain regions can be enhanced in length even if a gate electrode is lessened in thickness so as to lessen the surface of the gate electrode and a sccanning line in level difference. SOLUTION: Impurities are introduced using a side wall 15 and a gate electrode which is kept large in thickness yet and formed of a resist layer as a mask. Meanwhile, a semiconductor film 11P is covered with a gate electrode 13N in a P-type TFT forming region. After impurities are introduced into a first semiconductor film 11N, the gate electrode 13N is thinned together with the conductor film 130P. Therefore, even if the first gate electrode 13N is formed thick to make a side wall 15 long in a direction of channel so as to enhance a TFT in offset length, the gate electrode 13N is lessened in thickness after impurities are introduced, so that the gate electrode 13N is small in surface level difference.</p> |
