| 摘要 |
PROBLEM TO BE SOLVED: To provide the digital phase locked loop(PLL) circuit not requiring complicated algorithm, easy design and control, small jitter and high precision. SOLUTION: Delay step number control of a delay variable circuit 16 is conducted based not on phase comparison output information from a phase comparator circuit 14 but on frequency comparison output information from a frequency comparator circuit 11, and a load capacitance variable circuit of the delay variable circuit 16 is controlled mainly by the frequency comparison output information while using the frequency comparison output information as auxiliary information. Thus, the digital PLL not requiring complicated algorithm, easy design and control, small jitter and high precision is configured. |
