Method of driving ferroelectric gate transistor memory cell

摘要

A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage Vg to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage VW lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage Vg to the ferroelectric. The memory information is read out by applying a voltage VDR lower than the voltage VW and having a polarity opposite to that of the voltage Vg to the drain to read a drain current IDS.