发明名称 |
Methodology for developing product-specific interlayer dielectric polish processes |
摘要 |
A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.
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申请公布号 |
US5665199(A) |
申请公布日期 |
1997.09.09 |
申请号 |
US19950493972 |
申请日期 |
1995.06.23 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
SAHOTA, KASHMIR S.;AVANZINO, STEVEN C. |
分类号 |
H01L21/3105;H01L21/66;(IPC1-7):H01L21/306 |
主分类号 |
H01L21/3105 |
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地址 |
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