发明名称 |
Power reduction in a data processing system using pipeline registers and method therefor |
摘要 |
In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82). |
申请公布号 |
US5666300(A) |
申请公布日期 |
1997.09.09 |
申请号 |
US19940361405 |
申请日期 |
1994.12.22 |
申请人 |
MOTOROLA, INC. |
发明人 |
ADELMAN, JUDAH L.;GALANTI, DAVID;SALANT, YORAM |
分类号 |
G06F1/32;G06F7/544;G06F9/30;G06F9/302;G06F9/38;(IPC1-7):G06F7/38;G06F1/00 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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