发明名称 INFORMATION PROCESSING SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To realize electrical erasing leaving a batch erasing type EEPROM as it is mounted on a system without lowering the throughput of the system by providing an erasing control circuit in the batch erasing type EEPROM. SOLUTION: An erasing control circuit (LOGC) conducts erasing operation to an electrical batch erasing type EEPROM shown in the figure according to an erasing instruction from the outside, and performs at least one-time read operation to a non-volatile storage element in memory arrays (M-ARY) carrying out erasing operation. The continuation and stoppage of erasing operation are controlled on the basis of the read information. Accordingly, since EEPROM itself has an automatic function with the read of erasing confirmation, control from a microprocessor is conducted for a slight time only for instruction for erasing start, and the burden on the microprocessor is lightened remarkably, and the throughput of the system is not sacrificed.</p>
申请公布号 JPH09231787(A) 申请公布日期 1997.09.05
申请号 JP19970011820 申请日期 1997.01.06
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 SEKI KOICHI;WADA TAKESHI;MUTO TADASHI;KUBOTA YASURO;SHOJI KAZUYOSHI
分类号 G11C17/00;G06F15/78;G11C16/02;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/06;H01L21/824 主分类号 G11C17/00
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