摘要 |
<p>PROBLEM TO BE SOLVED: To sufficiently show the processing capacity of a processor and to realize miniaturization by narrowing the bus width of a processor bus rather than that of a memory bus and changing bus width with a selector. SOLUTION: The processor bus B1 with smaller bus width connects CPU 3 and a buffer 4 and the memory bus B2 with wider bus width connects the buffer 4 and a memory cell area 2. At the time of reading data or an instruction from the memory cell area 2, a latch 42 once holds the instruction and gives it to a selector 41. The selector 41 reduces bus width based on a control signal and gives data or the instruction to CPU 3. At the time of writing data from CPU 3 into the memory cell area 2, the selector 41 extends bus width based on the control signal and gives the data to the latch 42. The latch 42 temporarily latches data and gives it to the memory cell area 2. The control signal is given from CPU 3.</p> |