发明名称 CLOCK GENERATOR
摘要 PROBLEM TO BE SOLVED: To prevent the picture quality degradation of a display image by improving reproduction delay at an image transmission system. SOLUTION: When a first system time reference value (SCR) arrives, a counter 17 sets a count value S17 to the value of that SCR and afterwards, the number of cycles of system time clock (STC) is counted from this set value. Each time the SCR arrives, a phase comparator 12 reads the count value S17 at that moment and phase difference data S12 are outputted from the count value S17 and the value of the SCR. The phase difference data S12 are smoothed by an LPF 13 and inputted to a limiter 14. The limiter 14 outputs an output signal S13 of the LPF 13 after limiting it into the range of a prescribed threshold value. With an output signal S14 of the limiter 14 as a control signal, a VCO 15 decides an oscillation frequency and outputs a signal at the decided frequency to an STC output terminal 16 and the counter 17 as the STC.
申请公布号 JPH09233469(A) 申请公布日期 1997.09.05
申请号 JP19960033692 申请日期 1996.02.21
申请人 OKI ELECTRIC IND CO LTD 发明人 FUKUI KIYOSHI;NONAKA MASAHITO;NAKAI TOSHIHISA
分类号 H04N19/102;H03L7/093;H04N7/10;H04N7/24;H04N19/00;H04N19/134;H04N19/196;H04N19/423;H04N19/426;H04N19/70;H04N19/80;H04N19/82;H04N19/85;H04N21/438 主分类号 H04N19/102
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