| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL oscillation circuit capable of suppressing stably a jitter element through the use of simple configuration without using a digital clock oscillation circuit. SOLUTION: This PLL oscillation circuit is provided with a voltage controlled oscillator(VOC) 306 which oscillates and outputs a basic clock signal (f) on the basis of a clock oscillation signal (g) self-oscillated from a clock oscillator 209 and a clock signal CLK containing the jitter element to be transmitted and outputted. Here, a CPU 303 inputs a phase difference digital signal (b) containing phase difference information in the clock signal CLK and the clock oscillation signal (g), and outputs a frequency controlling digital signal (c) to show the voltage value of the basic clock signal (f), and a filter 305 suppresses the jitter element contained in the clock signal CLK for controlled voltage (d) and outputs filter control voltage (e). Thus, the frequency of the basic clock signal (f) is controlled, and clock synchronization with the clock signal CLK is established. |
