| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method of manufacturing a simplified thin film CMOS transistor suitable for a large screen, and to provide an element structure with which a parasitic capacitance can be controlled and characteristics can be improved. SOLUTION: A source layer 28a and a drain layer 28b are connected by a channel layer 42, and buffer layers 30a and 30b are formed on the overlapped part of the above-mentioned source layer 28a and the drain layer 28b. As a result, parasitic capacitance can be suppressed and characteristics can be improved. A transistor is manufactured as follows. After an N-type silicon layer 28, an insulating layer 30, a P-type silicon layer 32 and an insulating layer 34 have been formed, a P-type silicon layer 32 and an insulating layer 34 are patterned, and then the N-type silicon layer 28 and the insulating layer 30 are patterned. When a pattern is formed on the above-mentioned two layers, a channel layer 42, a gate insulating layer 38 and a gate electrode layer 40 are formed and patterned. As ions are not implanted, annealing is not necessary, the process of manufacturing can be simplified, and the generation of a thin film kink can be prevented. Also, the uniformity of dopant of this transistor is excellent as a whole, and it is suitable for the display of a large screen.</p> |
