| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit with which synchronizing speed can be further accelerated while suppressing the frequency of input signal to a phase frequency comparator(PFC) lower than an upper limit frequency processable in the PFC. SOLUTION: A reference signal fr is frequency-divided to 1/6 by a frequency divider 12a, converted into signals fr1-fr6 having mutually shifted phases and supplied to PFC 13a-13 later. Similarly, an output signal fv is frequency-divided to 1/6 by a frequency divider 12b, converted into signals fv1-fv6 having mutually shifted phases later and supplied to PFC 13a-13f. At the PFC 13a-13f, phase difference between the signals fr1-fr6 and the signals fv1-fv6 is extracted and corresponding to this phase difference, error signals PD1-PD6 are outputted. The signals PD1-PD6 are mixed at mixers 14a-14e and finally, an error signal PD is supplied to a VCO 11. Thus, even without increasing the input frequency to the PFC, the error signal can be supplied to the VCO a more frequently per time. |
