Struktur und Verfahren zur Integration von DMD mit Kontrollschallkreise aufweisenden Substraten

摘要

DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructue 213 on top of an underlying CMOS address circuit 126. The CMOS chip surface contains several processing artifacts 110, and 124, that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifiacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.