Semiconductor memory device having address transition detection circuit for controlling sense and latch operations

摘要

In a semiconductor memory device including: an address buffer (2) for generating an address signal (IADD) , a memory cell array (1) for generating a first data signal (D1) in response to the address signal, a sense amplifier circuit (6) for sensing the first data signal to generate a second data signal (D2) in response to a sense activation signal ( phi S), a data latch circuit (7) for latching the second data signal to generate a third data signal in response to a latch activation signal ( phi L ), an address transition detection circuit (8) for detecting a transition of the address signal to generate an address transition detection signal ( phi ATD), and a timing generating unit (10', 10'') for generating the sense activation signal and the latch activation signal, the timing generating unit is formed by a plurality of timing generating circuits (10-1, 10-1', 10-2, 10-3, 10-3') for prolonging the address transition detection signal by different delay times ( tau 1, tau 2, tau 3) to generate pulse width signals ( phi 1, phi 2, phi 3). The delay times have different characteristics depending upon a power supply voltage (VCC). Also, a logic circuit (11) logically adds the pulse width signals to each other to generate a logic signal ( phi S'). A pulse prolonging circuit (12, 13) prolongs the logic signal by a definite time to generate the sense activation signal, and a pulse generating circuit (14) generates the logic signal in response to a termination of the logic signal. <IMAGE>