Semiconductor device having multi-level wirings

摘要

A semiconductor device that has a feature in the spatial relationship between the wirings in a multi-level wirings and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wirings there exist intermediate insulating films that have a pattern which is the same as the pattern of the wirings. Because of this arrangement, the intermediate insulating film does not exist between the wirings on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wirings can be reduced markedly compared with a semiconductor device that has a structure in which the spaces between the wirings are filled with the intermediate films.