发明名称 Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
摘要 A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.
申请公布号 US5664117(A) 申请公布日期 1997.09.02
申请号 US19960603688 申请日期 1996.01.20
申请人 INTEL CORPORATION 发明人 SHAH, NILESH;AJANOVIC, JASMIN;DAHMANI, DAHMANE
分类号 G06F5/06;G06F13/40;(IPC1-7):G06F13/00 主分类号 G06F5/06
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