发明名称 High performance bus driving/receiving circuits, systems and methods
摘要 Circuitry 200 is provided for transmitting data between a first endpoint and a second endpoint and includes an information line 201 and a dummy line 205. Information transmission circuitry 202, 203, 204 is disposed at the first endpoint for transmitting information on information line 201, transmission circuitry 202, 203, 204 pulling information line 201 to a low voltage during transmission of information of a first logic state and charging information line 201 to a higher voltage during transmission of information of a second logic state. Charging circuitry 206, 207, 208 is disposed at the first endpoint for charging dummy line 205 to a reference voltage during transmission of information on information line 201, charging circuitry 206, 207, 208 charging dummy line 205 at a rate different from a rate at which transmission circuitry 202, 203, 204 charges information line 201 during transmission of information of the second logic state. Receiving circuitry 209 is disposed at the second endpoint for detecting a voltage difference between information line 201 and dummy line 205 and in response determining the logic state of transmitted data on information line 201.
申请公布号 US5663984(A) 申请公布日期 1997.09.02
申请号 US19950434656 申请日期 1995.05.04
申请人 CIRRUS LOGIC, INC. 发明人 RUNAS, MICHAEL E.
分类号 H04L25/02;(IPC1-7):H04L27/00 主分类号 H04L25/02
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