| 摘要 |
In a memory device such as a DRAM or multiport DRAM, each of a plurality of memory cells includes an access transistor with a gate connected to a word line and a storage capacitor with a storage node connected through the access transistor to a digit line. Data is transferred on the digit line to and from the storage capacitor when the word line is activated and the access transistor enabled thereby. According to the present invention, a timing control circuit is provided to control deactivation of the word line. The timing control circuit includes a digit-write/transfer model that simulates a read-write cycle in a DRAM or a serial write transfer operation in a multiport DRAM. The digit-write transfer model produces an output signal indicating the state of the modeled data transfer operation. The timing control circuit also includes a reference voltage circuit and a level comparator. The level comparator compares the model output signal to the reference voltage provided by the reference voltage circuit. The level comparator includes a sensitive analog multi-stage current mirror differential amplifier circuit and produces a signal input to a RAS timing chain circuit which deactivates the word line upon completion of the modeled data transfer operation.
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