发明名称 Process for producing multilayer wiring boards
摘要 An improved process for producing a multilayer wiring board that has a plurality of conductor patterns (2) and an interlevel dielectric layer (3) on at least one surface of a substrate (1), with via holes (5) or trench-like channels (8) being provided at specified sites of said interlevel dielectric layer (3) to establish an electrical interconnection between said conductor patterns (2), characterized in that prior to the provision of said via holes (5) or trench-like channels (8), a coating (4) having resistance to sandblasting is formed in a pattern over the interlevel dielectric layer (3) and then sandblasting is performed to remove the interlevel dielectric layer (3) in selected areas to form the via holes (5) or trench-like channels (8) and, thereafter, the coating (4) having resistance to sandblasting is removed, followed by the provision of a conductive layer (7). <IMAGE>
申请公布号 EP0793406(A1) 申请公布日期 1997.09.03
申请号 EP19970103255 申请日期 1997.02.27
申请人 TOKYO OHKA KOGYO CO., LTD. 发明人 TAKIGUCHI, YOSHIKAZU;OBIYA, HIROYUKI;TAKAHASHI, TORU;SHIROYAMA, TAISUKE;TAZAWA, KENJI
分类号 H05K3/00;H05K3/46 主分类号 H05K3/00
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