发明名称 |
VERTICAL DEFLECTION OUTPUT CIRCUIT |
摘要 |
PURPOSE:To drastically reduce the power consumed in vertical output transistors by supplying the current obtained through rectification and smoothing of a flyback pulse generated in secondary windings and the dc outputs from small signal low voltage windings to a vertical output circuit. |
申请公布号 |
JPS52127022(A) |
申请公布日期 |
1977.10.25 |
申请号 |
JP19760043552 |
申请日期 |
1976.04.19 |
申请人 |
HITACHI LTD |
发明人 |
INOUE FUMIO;MASUDA MICHIO |
分类号 |
H04N3/18;H04N3/16;H04N5/63 |
主分类号 |
H04N3/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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