发明名称 |
Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines |
摘要 |
A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.
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申请公布号 |
US5663913(A) |
申请公布日期 |
1997.09.02 |
申请号 |
US19960638373 |
申请日期 |
1996.04.26 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, HO-CHEOL;JANG, HYUN-SOON |
分类号 |
G11C11/41;G11C7/22;G11C11/409;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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