Semiconductor memory device

摘要

A DRAM is disclosed in which column address COL1 is taken in when signal /CAS falls at time t1, data D1 is output after period tCD has elapsed from the rise of signal /CAS at time t2, and output of data D1 is stopped after period tCDH has elapsed from the fall of signal /CAS at time t3. Therefore, upon interleave operations, data collision does not occur at the rise and fall of signal /CAS.