发明名称 |
Integrated circuit chip having built-in self measurement for PLL jitter and phase error |
摘要 |
A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values. |
申请公布号 |
US5663991(A) |
申请公布日期 |
1997.09.02 |
申请号 |
US19960613276 |
申请日期 |
1996.03.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KELKAR, RAM;NOVOF, ILYA IOSEPHOVICH;WYATT, STEPHEN DALE |
分类号 |
G01R29/26;G01R31/30;G01R31/317;G06F11/27;H03L7/081;(IPC1-7):H03D3/24 |
主分类号 |
G01R29/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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