发明名称 |
Apparatus and method for testing a memory array |
摘要 |
There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.
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申请公布号 |
US5663965(A) |
申请公布日期 |
1997.09.02 |
申请号 |
US19950539932 |
申请日期 |
1995.10.06 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP. |
发明人 |
SEYMOUR, EDWARD MICHAEL |
分类号 |
G11C29/40;(IPC1-7):G01R31/28;G11C7/00 |
主分类号 |
G11C29/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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