Internal timing method and circuit for programmable memories

摘要

A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.