MPEG2 standard digital video coder with scalable architecture

摘要

The coder has a module with a leading computer interface (611), and a picture element interface (641) for receiving picture element data from the data bus (643), There is a picture memory interface (651) for receiving and transmitting the picture data. There is also a discrete cosine transformation processor (671), a quantisation unit (673), a variable length coder (675) and a first-in-first-out buffer memory (677). An interface (679) is provided for storing the compressed pictures, in order, to produce a bit sequence of I pictures.