| 摘要 |
<p>A method (FIG 9, FIG 10) and apparatus (201) for implementing a zero order hold function (150) in the digital to analog conversion process (206) in a digital control system (FIG 2) reduces the phase lag contributed by the digital to analog conversion process (206) relative to a conventional implementation of the zero order hold function (150). The apparatus (201) for implementing the reduced phase lag zero order hold function (150) employs a digital signal processor (105), a plurality of digital buffers (202-204), a digital multiplexing element (207), and a digital to analog converter (206). Phase lag is reduced by generating, from the digital to analog converter (206), for a fraction of the sample period, a waveform (FIG 8) having a constant analog voltage with an amplitude which is scaled by the reciprocal of said fraction relative to a conventional zero order hold function (150). During the remainder of the sample period a substantially constant offset analog voltage is generated by the digital to analog converter (206). Alternatively, the time compression and amplitude scaling required to implement the reduced phase lag zero order hold function can be performed within the digital signal processor (105) in the digital control system (FIG 2). <IMAGE></p> |
