| 摘要 |
PURPOSE:To reduce the number of steps processed for each sampling period by dividing the processing for left and right channel digital data inputted for each prescribed sampling period into a block completed for each sampling period and a block completed at a period being a multiple of N of the period. CONSTITUTION:First and 3rd blocks 11, 13 are operated at a sampling frequency fS. Then the execution of a program for processing both blocks is finished till a succeeding data is inputted every time digital data LIN, RIN of left and right channels are inputted. On the other hand, a 2nd block 12 is operated at 1/N of the sampling frequency fS. Then the program is divided almost uniformly into 1/N and each of the program is implemented before and after the execution of the program for the 1st and 3rd blocks for each sampling period. Since the data processing circuit is controlled simultaneously by the same program, the number of program steps is decreased. |
