| 摘要 |
PURPOSE:To correctly decode the 1B-2B code without increasing the circuit scale by changing the phase of a clock by 180 deg. when it is detected that the coded pattern is equal to an inhibition pattern in a decoding mode of the data on a code (1B-2B) where 1 bit is converted into 2 bits. CONSTITUTION:The reproduction data on the M<2> code received from an input terminal 1 undergoes the waveform shaping through a reproduction process circuit 2 and is turned into the rectangular data. While a reproduction clock CLK0 is formed based on the rectangular data and the rectangular data is turned into the signal PBDA synchronous with the clock CLK0 to be obtained through the circuit 2. Both the signal PBDA land the clock CLK0 are supplied to an M<2> decoder 3. The CLK0 is also supplied to a flip-flop 4 and clocks CLK1 and CLK2 having different phases by 1808 deg. are obtained with a frequency equal to 1/2 as much as that of the clock CLK2. An error flag EF is supplied to a flip-flop 6 via an AND gate 7 when the pattern decoded by the decoder 3 is equal to an inhibition pattern. Then the states of selection signals SE and SE' are inverted and the output CLK3 of a selector 5 is switched between clocks CLK1 and CLK2. |
