发明名称 JIDOSHUHASUSEIGYOSOCHI
摘要 PURPOSE:To make an error small, and in addition, to simplify circuit configuration by providing a third integrator to integrate the output of a second integrator and a D/A converter to control the frequency conversion characteristic of a receiver on the basis of this integrated result. CONSTITUTION:The receiver 2 converts the frequency of a received signal, and inputs it to a phase quantizer 3. The phase quantizer 3 quantizes the phase of the received signal by using a reference signal from a digital VCO 8, and outputs it to a terminal 4, and simultaneously, it inputs it to a frequency error detector 5. The detector 5 outputs lead/lag as one-bit information. A first integrator 6 integrates the lead/lag, and outputs an overflow signal and a sign as two-bit information. The second integrator 7 integrates the sign when the overflow signal is generated. The integrated result is inputted to the VCO 8 and the third integrator 9. The integrator 9 integrates the output of the integrator 7 when the integrator 7 operates integral operation. The integrator 9 outputs the integrated result to the D/A converter 10. The output of the converter 10 controls the frequency conversion characteristic of the receiver 2.
申请公布号 JP2646879(B2) 申请公布日期 1997.08.27
申请号 JP19910079180 申请日期 1991.04.11
申请人 MATSUSHITA DENKI SANGYO KK 发明人 IGAWA KEIICHI
分类号 H03L7/093;H04B1/26 主分类号 H03L7/093
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