发明名称 |
Digital PLL circuit |
摘要 |
A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.
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申请公布号 |
US5661425(A) |
申请公布日期 |
1997.08.26 |
申请号 |
US19950440977 |
申请日期 |
1995.05.15 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
MINODA, HIDENORI;MATSUOKA, HIROYUKI;MATSUFUJI, KATSUAKI |
分类号 |
G11B19/247;G11B20/14;H03L7/099;H03L7/107;(IPC1-7):H03K5/13 |
主分类号 |
G11B19/247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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