发明名称 |
CACHE MEMORY |
摘要 |
<p>PROBLEM TO BE SOLVED: To dynamically use a high-speed operation or a low power consumption operation selectively corresponding to the frequency of a reference operation clock signal without depending on a command from the outside. SOLUTION: A start signal generation circuit 7 generates a start signal for starting the access of a data memory 2 corresponding to the frequency of the reference operation clock signal based on a reference operation clock signal and a reference pulse signal outputted from a reference pulse generator 6. Then, according to this start signal and the hit check of tag data, the low power consumption operation and the high-speed operation can be dynamically switched corresponding to the frequency of the reference operation clock signal.</p> |
申请公布号 |
JPH09223068(A) |
申请公布日期 |
1997.08.26 |
申请号 |
JP19960028103 |
申请日期 |
1996.02.15 |
申请人 |
TOSHIBA MICROELECTRON CORP;TOSHIBA CORP |
发明人 |
SHIRATORI TSUKASA;HAYAKAWA MASAYUKI |
分类号 |
G06F1/04;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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