| 摘要 |
<p>PROBLEM TO BE SOLVED: To speed up the clock access time in a read mode having CAS latency of 3 by receiving a clock signal, forming first and second internal clock signals in respective output latch control signal forming circuits and supplying these signals to output latches of first and second stages. SOLUTION: The first stage output larches OLs 10 to 1F are made to perform through-action in the first latency mode and latch action in the second and third latency modes. The second stage output latches OLs 20 to 2F are made to perform the through-action in the first and second latency modes and to the larch action in the third latency mode. Simultaneously, the clock signal CLK from the outside is received and the first and second internal clock signal OKs 10 to 13, OKs 20 to 23 are formed by the output latch control signal forming circuits OGs 10 to 13, 20 to 23 and are supplied to the output latches OLs 10 to 1F, 20 to 2F of the first and second stages. As a result, the clock access time is speeded up and the upper limit frequency is enhances.</p> |
