| 摘要 |
A semiconductor substrate layer is provided which includes a plurality of severed through holes (or metallized half vias) along an edge portion of the substrate layer. The bonding fingers of a leadframe are then formed into a down set (or up set) format and soldered to the substrate at the severed, plated through holes. This technique increases the contact area between the leadframe and the substrate. In addition, the down set (or up set) format of the leadframe bonding fingers decreases the stress built up due to CTE mismatch between the substrate and the leadframe.
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