| 摘要 |
<p>PROBLEM TO BE SOLVED: To restore phase relation with simple circuit constitution even when the phase relation is instantaneously changed. SOLUTION: Delay circuits 1-5 generate clock signals whose phases are respectively different based on input clock signals and F/Fs 6-11 respectively retime input data by the input clock signals and the clock signals from the delay circuits 1-5. The F/Fs 12-17 retime the output data of the F/Fs 6-11 by the clock signals of the next stage and exclusive OR circuits 18-23 compare the logic levels of the respective output data of the F/Fs 6-11 and the F/Fs 12-17 for performing retiming by the same clock signals. A clock selection control part 24 controls a selection circuit 25 so as to select the clock signals capable of surely retiming the input data among the input clock signals and the clock signals delayed in the delay circuits 1-5 based on the output signals of the exclusive OR circuits 18-23.</p> |
