发明名称 NONVOLATILE MEMORY HAVING MULTIBIT CORRESPONDING CELL OF TWO-LAYERED FLOATING GATE STRUCTURE AND ITS PROGRAMMING/ERASING/READING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To increase storage capacity, by making a first floating gate and a control gate which are formed on a source and a drain a readout part, and making a second floating gate and a program gate which are formed on a high impurity concentration layer an erasing part. SOLUTION: At the time of readout mode, the amount of a current flowing between a drain 3 and a source 2 is detected by applying a voltage to a control gate 5. The threshold voltage of a first floating gate 4A is detected by charges charged on second floating gates 4B1 , 4B2 , and stored information is read out. At the time of program mode, a voltage is applied to a program gate 62 , and the high impurity concentration layer 22 is grounded. Then FN tunneling is generated between a tunnel oxide film formation part 4B20 and the high impurity concentration layer 22, and implantation is performed to the second floating gate 4B2 . At this time, implantation is not performed to the second floating gate 4B1 by an insulating layer 10.</p>
申请公布号 JPH09223753(A) 申请公布日期 1997.08.26
申请号 JP19960030779 申请日期 1996.02.19
申请人 NIPPON MOTOROLA LTD 发明人 KOJIMA TOSHIAKI
分类号 G11C17/00;G11C11/56;G11C16/04;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824;G11C16/02 主分类号 G11C17/00
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