| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the area of the decoder section of a NAND memory circuit whose memory cell section is highly integrated. SOLUTION: This memory circuit is provided with a memory mat section 50 which is provided with plural sets of n-bit NAND memory cells 51 constituted of NAND-connected transistors corresponding to n bits and a word line driver 60 which drives plural sets of memory cells 51 using n word line drivers 61, 62, 63,...64. The word lines which are respectively installed in the plural sets of memory cells 51 and correspond to each other are connected to the same word line driver in the word line driver 60 in common. Thereby, it is unnecessary to equip the word line drivers of the same number as that of all word lines (all transistors).</p> |
