| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the complication of a signal processing by memory access by writing inputted data in an internal memory after acceptance signals are generated. SOLUTION: A read control part 15 generates read chip enable signals and a read address from first request signals outputted from a VLD 21, and when the read address reaches a prescribed level, generates second request signals and supplies them to an external memory controller 13. Then, when the acceptance signals to the second request signals are generated from the external memory controller 13, a write control part 17 generates a write address and write section signals from the acceptance signals. Further, an internal memory control part 19 performs control so as to write the data supplied from an external memory 11 corresponding to the write address and the write section signals generated from the write control part 17. In this case, utilization can be performed as a buffer controller corresponding to the speed of the input data as well.</p> |
