发明名称 GAZOSHINGOFUGOKASOCHINO2MENBATSUFUAMEMORIKIRIKAEHOHO
摘要 PURPOSE:To eliminate useless waiting period and to utilize the processing capability of a coding processing section to the utmost by starting a coding processing of other memory picture even when the other memory picture is under pre-processing after the coding processing of one memory picture is finished. CONSTITUTION:When pre-processing by one frame to one memory picture 31 is finished, the termination of the coding processing by one frame of other memory picture 32 is detected, the pre-processing is switched to the other memory picture 32 and the readout address for coding is controlled so as not to pass over the write address of the pre-processing and the pre-processing and the coding processing are switched independently. Even when the other memory picture 32 is subject to pre-processing after the coding processing of one memory picture 31 is finished in this way, the coding processing of the other memory picture is initiated, useless wait period of the coding processing is eliminated and frame elimination is reduced, the real time processing performance is enhanced and the average loading design is attained.
申请公布号 JP2644573(B2) 申请公布日期 1997.08.25
申请号 JP19890022640 申请日期 1989.02.02
申请人 NIPPON DENSHIN DENWA KK 发明人 NISHIMURA SHINJI;KURODA HIDEO;TSUCHA TOSHIO
分类号 H04N19/423;H03M7/30;H04N1/41;H04N7/24;H04N19/00;H04N19/85 主分类号 H04N19/423
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