发明名称 GAZOSHINGOFUKUGOKASOCHINO2MENBATSUFUAMEMORIKIRIKAEHOHO
摘要 PURPOSE:To eliminate useless waiting period and to utilize the processing capability of a decoding processing section to the utmost by starting a decoding processing of other memory picture even when the other memory picture is under post-processing after the decoding processing of one memory picture is finished. CONSTITUTION:When post-processing by one frame to one memory picture 31 is finished, the termination of the decoding processing by one frame of other memory picture 32 is detected, the post-processing is switched to the other memory picture 32 and the write address for decoding is controlled so as not to pass over the readout address of the post-processing and the post-processing and the decoding processing are switched independently. Even when the other memory picture 32 is subject to post-processing after the decoding processing of one memory picture 31 is finished in this way, the decoding processing of the other memory picture is initiated, useless wait period of the decoding processing is eliminated and frame elimination is reduced and the average loading design is attained.
申请公布号 JP2644574(B2) 申请公布日期 1997.08.25
申请号 JP19890022641 申请日期 1989.02.02
申请人 NIPPON DENSHIN DENWA KK 发明人 NISHIMURA SHINJI;KURODA HIDEO;TSUCHA TOSHIO
分类号 H04N19/102;H03M7/30;H04N1/41;H04N7/24;H04N19/00;H04N19/152;H04N19/423;H04N19/44;H04N19/85 主分类号 H04N19/102
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