METHOD OF OPERATING AN SRAM MOS TRANSISTOR STORAGE CELL

摘要

PCT No. PCT/DE96/02394 Sec. 371 Date Jun. 22, 1998 Sec. 102(e) Date Jun. 22, 1998 PCT Filed Dec. 12, 1996 PCT Pub. No. WO97/23878 PCT Pub. Date Jul. 3, 1997In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.